Design full adder using VHDL programming |

PROGRAM:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Full_Adder_Design is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         c : in STD_LOGIC;
         sum : out STD_LOGIC;
         carry : out STD_LOGIC
         );
end Full_Adder_Design;

architecture Full_Adder_Design_arc of Full_Adder_Design is
begin

    sum <= a xor b xor c;
    carry <= (a and b) or                
             (b and c) or
             (c and a);
            
end Full_Adder_Design_arc;

Half adder in VHDL using logical expressions |

PROGRAM:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Half_Adder is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         sum : out STD_LOGIC;
         carry : out STD_LOGIC
         );
end Half_Adder;

architecture Half_Adder_arc of Half_Adder is
begin

    sum <= a xor b;
    carry <= a and b;

end Half_Adder_arc;

AND gate design using VHDL programming language

Program -

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity and_gate is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end and_gate;

architecture and_gate_arc of and_gate is
begin

    dout <= a and b;

end and_gate_arc;