2 to 4 decoder using VHDL programming language |

PROGRAM :

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder2_4 is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         w : out STD_LOGIC;
         x : out STD_LOGIC;
         y : out STD_LOGIC;
         z : out STD_LOGIC
         );
end decoder2_4;

architecture decoder2_4_arc of decoder2_4 is
begin

    w <= (not a) and (not b);
    x <= (not a) and b;
    y <= (a and (not b));
    z <= a and b;

end decoder2_4_arc;