AND gate design using VHDL programming language

Program -

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity and_gate is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end and_gate;

architecture and_gate_arc of and_gate is
begin

    dout <= a and b;

end and_gate_arc;