Design of 1 bit comparator using VHDL

PROGRAM:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity comparator is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         equal : out STD_LOGIC;
         lower : out STD_LOGIC;
         greater : out STD_LOGIC
         );
end comparator;

architecture comparator_arc of comparator is
begin

    equal <= a xnor b;
    lower <= (not a) and b;
    greater <= a and (not b);

end comparator_arc;