Half adder in VHDL using logical expressions |

PROGRAM:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Half_Adder is
     port(
         a : in STD_LOGIC;
         b : in STD_LOGIC;
         sum : out STD_LOGIC;
         carry : out STD_LOGIC
         );
end Half_Adder;

architecture Half_Adder_arc of Half_Adder is
begin

    sum <= a xor b;
    carry <= a and b;

end Half_Adder_arc;